MyHDL: Refactor conversion

by Keerthan Jaic for Python Software Foundation

MyHDL relies on parsing the abstract syntax tree (AST) of various objects in order to generate HDL. The target HDLs(Verilog/VHDL) have various lexical and semantic differences which make conversion a tricky process. In it’s current state, a large part of MyHDL’s conversion logic is duplicated across the various ast.NodeVisitors. The primary goal of this project is to make MyHDL’s conversion modules more robust.